1). Field
Embodiments relate generally to a method of making materials for dielectric substrate layers and underfills, and more specifically in the substrate imprinting process.
2). Discussion of Related Art
Substrate imprinting technology is a process for packaging substrate fabrication. A substrate includes non-conductive material which a circuitry pattern is printed. A circuitry pattern is directly printed into the dielectric layer by imprinting a build-up layer. The current state of the art for substrate manufacture utilizes a thermosetting epoxy dielectric film upon which a layer of copper is plated. The circuitry is obtained by use of a sacrificial photo-definable layer, which after being developed serves as the mask for etching the exposed copper and dielectric material. The photo-definable layer is then removed and the dielectric layer is cured to form a rigid pattern.
In the current state of the art chips are electrically connected “facedown” with its electronic components in direct contact with the conductive bumps on the chip-bond pads on the substrates or circuit boards. Using the entire area of the die, this direct connection between chip and substrate provides a flexible and mechanically rugged interconnection method. An underfill is a dielectric adhesive material to enhance the performance of a chip by interposing between a chip and a substrate. An underfill layer serves several purposes. The underfill provides mechanical strength to the assembly and protects the bumps from moisture or other environmental hazards. It reduces joint stress and improves reliability of the structure, allowing low cost substrates to be used. Most importantly, it compensates for any thermal expansion difference between the chip and the substrate. The underfill mechanically “locks together” chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps.
The substrate and underfill are insulators and critical in the process of electronic packaging. A low thermal expansion coefficient (CTE) in the underfill prevents a thermo-mechanical mismatch between the die and the substrate. In particular, a low thermal expansion coefficient of expansion in the underfill prevents interference with the soldering joint CTE (e.g. about 25 ppm/° C.). An underfill with a high CTE (e.g. 70-85 ppm/° C.) may cause cracking and delamination of the structure during operation. A material with high-temperature stability and superior thermal conductivity helps to maintain integrity in electronic packaging by remaining stable while dissipating heat faster.
Such rigorous demands on materials have prompted discovery and development of alternatives to epoxy-based materials. Specifically, the development of packaging materials with improved toughness and stress management for improved reliability, reduced dielectric constant for miniaturization and higher process frequencies, and rapid curing for increased production (units per hour/UPH) and reduced cost. For new materials to be attractive, they must be compatible with existing processes and equipment and must be available at low cost.
There is growing interest in thermosetting polyimide materials for use in packaging applications. However, there remains a need to reduce the CTE of the thermoset polyimide resin to match the low CTE of the silicon die to be used as an underfill. One method to reduce CTE is addition of filler materials, but filler particles lead to higher viscosity, decreased strain to failure and have the potential for excursions cue to large filler particles and filler settling.
Another known shortcoming of polyimide materials is the incompatible thermoplastic and thermosetting properties with existing processes and equipment. Thermoplastic polyimides require injection molding/curing at high temperatures and pressures, typically above 400° C. Current polyimide cross-linking technology is based on thermally induced reaction of unsaturated groups such as ethynyl and phenyl leading to a complex crosslinked product. For example, although nadimide resins, developed by NASA and others for aerospace and electronics applications, have good mechanical properties, the curing onset temperature is at least 200° C., making it out of range of the current processes used in the manufacturing of most microelectronic devices. Thus, there is a technology gap that prevents widespread use of cross-linking polyimides in microelectronics applications, namely processability and high curing temperatures.